Electro-optical device, driver circuit for electro-optical device, drive method for driving electro-optical device, and electronic equipment

ABSTRACT

An image signal processor circuit outputs image signals. A data line driver circuit generates sampling control signals to sample the image signals, by using a clock and an enable signal. A timing generator sets active periods of the enable signal which make the sampling possible, in periods which are other than periods including the rise or fall timings of the clock. Thus, the clock neither rises nor falls at timings at which the image signals are sampled, so that high frequency noise ascribable to the clock can be reduced or prevented from mixing into the image signals.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates to an electro-optical device of anactive matrix scheme, a driver circuit for an electro-optical device, adrive method to drive an electrooptical device, and an electronicequipment.

[0003] 2. Description of Related Art

[0004] In general, a related art electro-optical device, such as aliquid crystal device which presents a predetermined display byemploying a liquid crystal as an electro-optical substance, is soconstructed that the liquid crystal is sandwiched in between a pair ofsubstrates. Particularly in an electro-optical device, such as a liquidcrystal device of an active-matrix drive scheme based on TFT drive, TFDdrive or the like, a TFT array substrate or the like is overlaid withlarge numbers of scanning lines and data lines which are respectivelyarrayed vertically and laterally, a large number of pixel electrodeswhich are disposed in correspondence with the intersection points of thescanning lines and the data lines, and so forth.

[0005] The individual scanning lines are sequentially fed with scanningsignals from a scanning line driver circuit. On the other hand, the datalines are fed with image signals by a sampling circuit, which is drivenby a data line driver circuit. More specifically, the data line drivercircuit is constructed so as to feed a sampling circuit, by which imagesignals on an image signal line are sampled for the respective datalines, with sampling circuit drive signals in parallel with thesequential feed operations of the scanning signals.

[0006] The data line driver circuit includes, in general, a plurality oflatch circuits (a shift register circuit), which sequentially shift atransfer signal fed at the outset of a horizontal scanning period inaccordance with a clock signal, and which output the shifted signals asthe sampling signals. Likewise, the scanning line driver circuitincludes a plurality of latch circuits, which sequentially shift atransfer signal fed at the outset of a vertical scanning period inaccordance with a clock signal, and which output the shifted signals asthe scanning signals. The sampling circuit includes sampling switcheswhich are disposed for the respective data lines, and by which the imagesignals fed from outside are sampled in accordance with the samplingsignals based on the data line driver circuit, so as to be fed to thecorresponding data lines.

[0007] Accordingly, the sampling signals of the respective data linesneed to be generated exclusively from one another. Nevertheless, thesampling signals are sometimes outputted in overlapping fashion for anyreason. Then, the image signal which needs to be sampled by one of thedata lines is also sampled by the data line adjacent to this line. Thisresults in the problem that so-called “ghost”, “cross-talk” or the likeoccurs to degrade a display quality.

[0008] The related art includes a technique to cope with the heightenedfrequency of dot clocks, such that an image signal of one loop issubjected to serial-to-parallel conversion (phase expansion) into aplurality of m loops, and the resulting image signals of the m loops aresimultaneously sampled in accordance with a sampling signal so as to befed onto m data lines. When the sampling signal is outputted inoverlapping fashion in such a technique, the ghost, the cross-talk orthe like appears in units of m lines, and hence, degradation in adisplay quality becomes a more serious problem.

[0009] Therefore, a related art enable circuit can be introduced inorder to reduce or prevent the sampling signal from overlapping. Theenable circuit includes a technique such that, in order to reduce orprevent the sampling switches from sampling image signals in accordancewith successive sampling circuit drive signals which overlap on a timeaxis, the logical products between an enabling clock signal called an“enable signal” and the respective sampling circuit drive signals aretaken, thereby to narrow the pulse width of each of the sampling circuitdrive signals to the pulse width of the enable signal.

[0010] Some time interval is set as a temporal margin between the twosuccessive sampling circuit drive signals by limiting the pulse width inthis manner. Therefore, even when adverse effects such as ONresistances, wiring resistances, time constants, capacitances and delaytimes in active elements and various wiring lines of TFTs or the like,which constitute the sampling circuit, the data line driver circuit,etc., are relatively intensified with high frequency drive, the adverseeffect can be partially or completely absorbed by the temporal marginstated above.

[0011] As a result, it is possible to reduce or efficiently prevent theso-called “cross-talk” or “ghost” from appearing between the data lineswhich are adjacent to each other, in a case where the image signals arenot phase-expanded, or between the data lines which are connected to theidentical image signal and which are successively driven, in a casewhere the image signals are phase-expanded.

[0012] Meanwhile, the above mentioned shift register circuit isconstructed so as to generate transfer signals at individual stages onthe basis of an X-side clock signal CLX which is inputted from an imagesignal processor circuit located outside and which serves as thereference of horizontal scanning (and the inverted signal CLX_(inv)thereof), and an enable signal ENB, and to output the transfer signalsas the sampling circuit drive signals to the sampling switches which areconnected to the corresponding scanning lines, respectively.

[0013] However, when the rises or falls of the clock signal CLX or theinverted signal CLX_(inv) thereof and the enable signal ENB occurssubstantially at the same time, the level of high frequency noise whichmixes into the image signal to be fed to the data line becomesconspicuously high. The high frequency noise is displayed as a verticalline blur on a screen, and incurs the problem of degrading a screenquality.

SUMMARY OF THE INVENTION

[0014] The present invention address the above and/or other problems,and provides an electro-optical device and an electronic equipment inwhich the logical status of a clock signal CLX or the inverted signalCLX_(inv) thereof is prevented from changing in an active enable signalperiod and a period vicinal thereto, whereby the level of noise to bemixed into an image signal can be lowered to suppress a vertical lineblur.

[0015] An electro-optical device according to the present inventionincludes a plurality of scanning lines and a plurality of data lines,switching elements which are disposed in correspondence withintersection parts between the scanning lines and the data lines, pixelelectrodes which are disposed in correspondence with the switchingelements, and video signal lines which transmit image signals. Further,the device includes a data line drive device to sample the image signalstransferred by the video signal lines and feeding them to the datalines, by using a clock which serves as reference of horizontal scanningand an enable signal which determines timings to feed the image signalsto the data lines, and a timing generation device to set active periodsof the enable signal which make the sampling of the image signalspossible, in periods which do not include timings of rise or fall of theclock.

[0016] According to such a construction, the data line drive devicesamples the image signals transferred via the video signal lines andfeeds them to the individual data lines by using the reference clock ofthe horizontal scanning and the enable signal. The timing generationdevice sets active periods of the enable signal which make the samplingof the image signals possible, in the periods which do not include thetimings of the rise or fall of the clock. That is, neither the rise norfall of the clock arises within the active periods of the enable signalwhich sets sampling periods. Accordingly, high frequency noisesascribable to the rise and fall of the clock can be reduced or preventedfrom mixing into the image signals in the periods in which the imagesignals are being fed to the data lines. Since the timing of the rise orfall of the clock and that of the rise or fall of the enable signal donot coincide, it does not occur that the noises of both the clock andthe enable signal are superposed to drastically enlarge the noise levelof the image signals. Thus, the level of noise to be mixed into theimage signals can be reduced to prevent line blurs in a verticaldirection from being displayed on a screen and to enhance a screenquality.

[0017] The electro-optical device is provided such that the timinggeneration device sets the active periods of the enable signal, inperiods which are other than a period of predetermined width includingthe timing of the rise or fall of the clock.

[0018] According to such a construction, the rise and fall of the enablesignal arise at timings, which are distant from the rise and fall of theclock more than the period of the predetermined width. Accordingly, thelevel of the sum between noise ascribable to the clock and noiseascribable to the enable signal is comparatively small, so that thelevel of high frequency noise to be mixed into the image signals whichare fed to the data lines is sufficiently reduced.

[0019] The electro-optical device is provided such that the period ofthe predetermined width is a period, which is distant from the timing ofthe rise or fall of the clock more than 15 nanoseconds.

[0020] According to such a construction, the influences of noisesascribable to the rises or falls of the enable signal and the clock aresufficiently relieved, so that image signals of high screen quality canbe obtained.

[0021] The electro-optical device is provided such that the enablesignal has a plurality of active periods within one cycle of the clock,which serves as the reference of the horizontal scanning.

[0022] According to such a construction, the image signals can be fed toa plurality of data lines based on the enable signals in time divisionwithin one cycle of the clock, so that a clock frequency can be lowered.

[0023] An electronic equipment according to the present inventionincludes the above electro-optical device as the image formation device.

[0024] According to such a construction, the high frequency noises arereduced or prevented from mixing into the image signals in the aboveelectro-optical device, so that an image of high image quality free fromline blurs can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a schematic showing an electro-optical device accordingto a first exemplary embodiment of the present invention;

[0026]FIG. 2 is a perspective view showing the construction of a liquidcrystal panel 100 in FIG. 1;

[0027]FIG. 3 is a sectional view taken along plane A-A′ in FIG. 2;

[0028]FIG. 4 is a schematic circuit diagram showing a practicableconstruction of a data line driver circuit 140 in FIG. 1;

[0029]FIG. 5 is a timing chart showing various signals;

[0030]FIG. 6 is a timing chart showing a clock CLK and enable signalsENB1 to ENB4 in the case when image signals are fed to four data linesin time division within one clock CLK period;

[0031]FIG. 7 is a schematic showing an electronic equipment according tothe present invention;

[0032]FIG. 8 is a schematic showing another electronic equipmentaccording to the present invention; and

[0033]FIG. 9 is a schematic showing still another electronic equipmentaccording to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0034] Exemplary embodiments of the present invention are describedbelow with reference to the drawings. FIG. 1 is a schematic showing anelectro-optical device according to a first exemplary embodiment of thepresent invention. This exemplary embodiment is an example in which theinvention is applied to a liquid crystal device employing a liquidcrystal as an electro-optical substance.

[0035] In this exemplary embodiment, the logical status of a clocksignal CLX or the inverted signal CLX_(inv) thereof is prevented fromchanging at a timing at which image signals are fed to data lines, thatis, in the active period of an enable signal and a period vicinalthereto in which the enable signal permits the feed of the image signalsto the data lines, whereby the level of noise to be mixed into the imagesignals is lowered.

[0036] As shown in FIG. 1, the liquid crystal device includes a liquidcrystal panel 100, a timing generator 200, and an image signal processorcircuit 300. Among them, the timing generator 200 outputs timingsignals, control signals, etc., which are used in various portions. AnS/P conversion circuit 302 in the image signal processor circuit 300subjects an inputted image signal Video of one loop toserial-to-parallel conversion and outputs the resulting image signals ofsix loops in order to write them on the basis of phase expansion. Thereason why the image signal is subjected to the serial-to-parallelconversion into the six loops is that, in a sampling circuit 150, a timeperiod to apply the image signal to the source region of a thin filmtransistor (hereinafter “TFT”) which constructs each sampling switch 151is lengthened to sufficiently secure a sampling time period andcharge/discharge time periods.

[0037] An amplifier/inverter circuit 304 inverts image signals resultingfrom the serial-to-parallel conversion which need to be inverted, andthereafter amplifies the inverted image signals as necessity, so as tofeed as image signals VID1 to VID6 to the liquid crystal panel 100 inparallel. Whether or not the image signals are inverted is generallydetermined in accordance with whether a scheme to apply data signals isbased on polarity inversion in units of scanning lines 112, polarityinversion in units of data lines 114 or polarity inversion in pixelunits, and the cycle of the inversion is set at one horizontal scanningperiod or dot clock cycle. This exemplary embodiment is described belowby taking the case of the polarity inversion in units of the scanninglines 112 as an example for the sake of convenience, but the presentinvention shall not be construed to be restricted thereto.

[0038] The “polarity inversion” signifies to alternately invert thevoltage levels of the image signals to a positive polarity and anegative polarity with a reference potential set at the center potentialof the amplitudes of the image signals. Timings at which the imagesignals VID1 to VID6 of the six loops are fed to the liquid crystalpanel 100 are simultaneous in the liquid crystal device shown in FIG. 1,but they may well be sequentially shifted in synchronism with dotclocks. In this case, the image signals of the six loops aresequentially sampled by a sampling circuit described below.

[0039]FIG. 2 is a perspective view showing the construction of theliquid crystal panel 100 in FIG. 1, while FIG. 3 is a sectional viewtaken along plane A-A′ in FIG. 2.

[0040] The liquid crystal panel 100 is so constructed that an elementsubstrate 101 formed with various elements, pixel electrodes 118, etc.,and a counter substrate 102 provided with a counter electrode 108, etc.,are stuck together, with a predetermined gap held therebetween by asealing member 104 containing spacers (not shown) and with theirelectrode formation surfaces opposing each other, and that a liquidcrystal 105 of, for example, TN (Twisted Nematic) type is enclosed inthe gap as an electro-optical substance.

[0041] Glass, a semiconductor, quartz or the like is employed for theelement substrate 101, while glass or the like is employed for thecounter substrate 102. In a case where an opaque substrate is employedas the element substrate 101, the liquid crystal panel is used as areflection type, not as a transmission type. The sealing member 104 isformed along the peripheral edge of the counter substrate 102, and it ispartially opened in order to enclose the liquid crystal 105. Therefore,after the liquid crystal 105 has been enclosed, the open part is sealedby a sealant 106.

[0042] Next, a data line driver circuit described below is formed on thecounter surface of the element substrate 101 and in a region 140, onelatus outside of the sealing member 104, so as to output samplingsignals. Further, image signal lines, the sampling circuit, etc., maywell be formed in the region 150 of the latus in the vicinity of thesealing member 104 to-be-formed. On the other hand, a plurality of mountterminals 107 are formed at the outer peripheral parts of the latus soas to input various signals from external circuits (not shown).

[0043] Scanning line driver circuits are respectively formed in theregions 130 of two latera adjacent to the above latus, so as to drivethe scanning lines from both sides. If the delay of scanning signals tobe fed to the scanning lines does not pose a problem, a construction inwhich only one scanning line driver circuit is formed on one side maywell be adopted.

[0044] The counter electrode 108 provided on the counter substrate 102is constructed so as electrically connected with the element substrate101 by a conductive material at, at least, one of the four corners of asealing portion by which the counter substrate 102 is stuck with theelement substrate 101.

[0045] Further, if necessary, colored layers (color filters) areprovided in the regions of the counter substrate 102 opposing to thepixel electrodes 118, though not especially illustrated. However, in acase where the liquid crystal panel is applied for the use of colorlight modulation as in a multiple-plate type projector described below,the counter substrate 102 need not be formed with the colored layers.

[0046] Orientation films (omitted from FIG. 3) subjected to rubbingtreatment are respectively provided on the opposing surfaces of theelement substrate 101 and the counter substrate 102. Polarizers (notshown) conforming to the orientation directions of the orientation filmsare respectively disposed on the rear surface sides of the substrates101, 102. In FIG. 3, although the counter electrode 108, pixelelectrodes 118, mount terminals 107, etc. are made thick as a convenientmeasure to clarify their formation positions, they are actually thinenough to be neglected relative to the substrates.

[0047] The liquid crystal panel 100 is formed on the element substratewith the plurality of scanning lines 112 arrayed in parallel in anX-direction as shown in FIG. 1, and with the plurality of data lines 114in parallel in a Y-direction orthogonal to the X-direction. At theintersection points between the scanning lines 112 and the data lines114, the gate electrodes of TFTs 116, which are switches to controlindividual pixels, are connected to the scanning lines 112, while thesource electrodes of the TFTs 116 are connected to the data lines 114,and the drain electrodes of the TFTs 116 are connected to the pixelelectrodes 118. In addition, the pixels are respectively constituted bythe pixel electrodes 118, the common electrode formed on the countersubstrate, and the liquid crystal held between both of these electrodes,with the result that they are arrayed in the shape of a matrix incorrespondence with the intersection points between the scanning lines112 and the data lines 114. Incidentally, a storage capacitor (notshown) may well be further formed electrically in parallel with theliquid crystal held between the corresponding pixel electrode 118 andthe common electrode for every pixel.

[0048] A driver circuit 120 includes, at least, the scanning line drivercircuit 130, the data line driver circuit 140 and the sampling circuit150. The constituent elements of the driver circuit 120 are constructedby combining P-channel TFTs and N-channel TFTs which are formed by amanufacturing process common to that of the TFTs 116 for driving thepixels, so that the enhancement of a manufacturing efficiency, thelowering of a manufacturing cost, the homogenization of elementcharacteristics, etc., are attained.

[0049]FIG. 4 is a schematic circuit diagram showing a practicableconstruction of the data line driver circuit 140 in FIG. 1.

[0050] The data line driver circuit 140 operates so that a transferstart pulse DX-R or DX-L fed at the outset of a horizontal scanningperiod is sequentially shifted in accordance with the clock signal CLXand the inverted clock signal CLX_(inv) thereof, thereby to output thesampling signals S1 to Sn in a predetermined sequence.

[0051] The clock signal CLX as well as the inverted clock signalCLX_(inv) thereof, the transfer start pulse DX-R (DX-L) and enablesignals (pulse width limitation signals) ENB1, ENB2 to be fed to thedata line driver circuit 140 are all fed in synchronism with the imagesignals VID1 to VID6 by the timing generator 200 in FIG. 1. Actuallyused as these signals are signals obtained in such a way that low logicamplitude signals fed from the timing generator 200 are converted intohigh logic amplitude signals by level shifters (not shown). The reasonwhy logic amplitudes are converted in this manner, is that the timinggenerator 200 for feeding the various signals to the liquid crystalpanel 100 is generally constructed of CMOS circuits and thereforeproduces output voltages of about 3 to 5 V, whereas the constituentelements of the data line driver circuit 140 are TFTs formed by the sameprocess as that of the TFTs 116 to drive the pixels and thereforerequire comparatively high operating voltages of about 12 V.

[0052] The data line driver circuit 140 includes latch circuits 1430which are connected in (n+1) stages. One latch circuit 1430 latches andoutputs the last input level and feeds it as the input signal of thelatch circuit 1430 located at the succeeding stage at the time of thelevel transitions (rise and fall) of the clock signal CLX and theinverted clock signal CLX_(inv) thereof.

[0053] Each latch circuit 1430 is capable of transfers in both thedirections of an R-direction and an L-direction in the figure. In caseof the R-directional transfer, the transfer start pulse DX-R is inputtedfrom the left side of the latch circuit 1430, whereas in case of theL-directional transfer, the transfer start pulse DX-L is inputted fromthe right side of the latch circuit 1430. Therefore, the “succeedingstage” signifies the right side in the case of the R-directionaltransfer, and the left side in the case of the L-directional transfer.In driving the data line driver circuit 140 in both the directions, theenable signals ENB1, ENB2 need not be changed-over in accordance withthe transfer directions by setting the number n of stages at an oddnumber, so that the load of the external circuit can be lowered.

[0054] Letter i is for generalizing the latch circuits 1430 of the firststage to the (n+1)th stage in the description. The data line drivercircuit in FIG. 4 is capable of the transfers in both the directions. Asignal Si′ (a signal outputted from the latch circuit 1430 of the ithstage in the case of the R-directional transfer, or a signal outputtedfrom the latch circuit 1430 of the (i+1)th stage in the case of theL-directional transfer) is fed to the first input node of a 3-input NANDcircuit 1464. The second input node of the NAND circuit 1464 is fed withthe enable signal ENB1 for the ordinal number i being odd, or with theenable signal ENB2 for the ordinal number i being even. Further, thethird input node of the NAND circuit 1464 is fed with the output signalof a NAND circuit 1462, more specifically, the negative logical productsignal of the enable signals ENB1 and ENB2.

[0055] The enable signals ENB1, ENB2 are signals which are used in orderto prevent the adjacent ones of the signals S1′ to Sn′ fromsimultaneously becoming an H level, each of which has a pulse widthshorter than the half cycle of the clock signal CLX (or inverted clocksignal CLX_(inv)), and which ought not to overlap each other.

[0056] The output signals of the NAND circuits 1464 corresponding to theindividual stages are inverted by inverters 1466, and the invertedsignals are outputted as the sampling signals S1 to Sn of the data linedriver circuit 140, respectively. Inverters 1466 may well be configuredof an inverter of a single stage, or inverters of a plurality of stages,such as three stages or five stages.

[0057] In this exemplary embodiment, the enable signals ENB1, ENB2 areset at L level periods disabling the sampling, at the rise or falltimings of the clocks CLK, CLK_(inv) and in a period vicinal thereto bythe timing generator 200.

[0058]FIG. 5 is a timing chart showing various signals.

[0059] As shown in FIG. 5, the enable signals ENB1, ENB2 rise after aperiod “tb” since the rise timing of the clock CLX (the fall timing ofthe clock CLX_(inv)), and they fall before a period “tf” since the falltiming of the clock CLX (the rise timing of the clock CLX_(inv)). Inthis exemplary embodiment, the periods “tb”, “tf” are set at timeperiods of, for example, at least 15 nanoseconds. Alternatively, theyare set at time periods of 15 to 20 nanoseconds.

[0060] As stated below, the image signals are sampled and fed to thedata lines in the H periods of the enable signals ENB1, ENB2. Due totiming settings in FIG. 5, accordingly, neither of the clocks CLX,CLX_(inv) rises or falls in the periods in which the image signals aresampled and fed to the data lines, so that high frequency noiseascribable to the rise or fall is reduced or prevented from mixing intothe image signals.

[0061] Assuming that the rise and fall timings of the enable signalsENB1, ENB2 and the rise or fall timings of the clocks CLX, CLX_(inv)arise in proximity, the high frequency noises of both the signals arecombined to greatly affect the image signals. However, Since the riseand fall timings of the enable signals ENB 1, ENB2 are set at thetimings which are sufficiently distant from the rise or fall timings ofthe clocks CLX, CLX_(inv), the levels of the high frequency noises to bemixed into the image signals can be relieved.

[0062] Referring back to FIG. 1, the sampling circuit 150 sets every sixdata lines 114 as one group (block), and it samples the respective imagesignals VID1 to VID6 and feeds them to the data lines 114 belonging tosuch groups, in accordance with the sampling signals S1 to Sn. Morespecifically, the sampling circuit 150 includes the switches 151, whichare disposed for the respective data lines 114. Each of the switches 151is interposed between one end of the corresponding data line 114 and asignal line which is fed with any of the image signals VID1 to VID6, andits gate is fed with the sampling signal.

[0063] The scanning line driver circuit 130 has basically the sameconstruction as that of the data line driver circuit 140, except thatthe direction of leading out the output signals, and signals to beinputted are different. More specifically, the scanning line drivercircuit 130 is such that the data line driver circuit 150 is arrangedafter being turned 90 degrees counterclockwise. As shown in FIG. 1, apulse DY-D (DY-U) and a transfer control signal D (U) are inputted tothis circuit 130 instead of the pulse DX-R (DX-L) and the transfercontrol signal R (L), and a clock signal CLY and the inverted clocksignal CLY_(inv) thereof are inputted for every horizontal scanningperiod instead of the clock signal CLX and the inverted clock signalCLX_(inv) thereof.

[0064] In a case where a vertical scanning direction is the downdirection, the pulse DY-D is fed at the outset of a vertical scanningperiod, and the transfer control signal D is activated. In contrast, ina case where the vertical scanning direction is the up direction, thepulse DY-U is fed at the outset of the vertical scanning period, and thetransfer control signal U is activated. The clock signal CLY, theinverted clock signal CLY_(inv) thereof and the pulse DY-U (or DY-D) arefed in synchronism with the image signals VID1 to VID6 by the timinggenerator 200 in FIG. 1. Further, these signals and the transfer controlsignal R (L) have all been converted into signals of high logicamplitudes by level shifters (not shown).

[0065] By setting the frequencies of these clock signals to be low, itis sufficiently possible that the scanning signals which are fed to theadjacent ones of the scanning lines be substantially reduced orprevented from overlapping. Therefore, no problem is posed even when thescanning line driver circuit 130 is endowed with a simple constructionwhich is based on a NAND circuit to narrow a pulse width, and aninverter succeeding it.

[0066] The operation of an exemplary embodiment thus constructed isdescribed below. In the ensuing description, it is assumed for the sakeof convenience that the vertical scanning direction be the downdirection, while the horizontal scanning direction be the rightward (R)direction.

[0067] The scanning line driver circuit 130 is fed with the pulse DY-Dat the outset of a vertical scanning period, and this pulse DY-D issequentially shifted by the clock signal CLY and the inverted clocksignal CLY_(inv) thereof so as to be outputted to the respectivescanning lines 112. Thus, the plurality of scanning lines 112 areselected in the down direction in line sequence one by one.

[0068] Due to the image signal processor circuit 300, the image signalVideo of one loop is distributed into the image signals VID1 to VID6 andis lengthened 6 times with respect to a time axis as shown in FIG. 5.Further, at the outset of a period in which a certain one of thescanning lines is selected, that is, at the outset of a horizontalscanning period, the data line driver circuit 140 is fed with thetransfer start pulse DX-R as shown in the figure.

[0069] In an ordinary operation, the enable signals ENB1, ENB2 are fedfrom the timing generator 200 so that, as shown in FIG. 5, the H level(active) periods thereof may not overlap each other. Therefore, theoutput signal of the NAND circuit 1462 in FIG. 4 continues to be at theH level and does not transits to an L level. For this reason, the outputof the NAND circuit 1464 depends upon only the signal Si and the enablesignal ENB1, for the ordinal number i being odd, and it depends upononly the signal Si and the enable signal ENB2, for the ordinal number ibeing even.

[0070] Therefore, the signals S1′ to Sn′, which are obtained in such away that the transfer start pulse DX-R fed at the outset is sequentiallyshifted for every half cycle of the clock signal CLX as well as theinverted clock signal CLX_(inv) thereof by the latch circuits 1430 ofthe first stage to the nth stage, are limited within the H level periodsSMPa of the enable signals ENB1, ENB2. They are sequentially outputtedas the sampling signals S1 to Sn as shown in FIG. 5.

[0071] When the sampling signal S1 has become the H level, the imagesignals VID1 to VID6 are respectively sampled onto the six data lines114 belonging to this group, and these image signals VID1 to VID6 arerespectively written into the six pixels intersecting with the scanningline 112 selected at the current time, by the corresponding TFTs 116.Subsequently, when the sampling signal S2 has become the H level, theimage signals VID1 to VID6 are respectively sampled onto the next sixdata lines 114 on this occasion, and these image signals VID1 to VID6are respectively written into the six pixels intersecting with thescanning line 112 selected at that time, by the corresponding TFTs 116.

[0072] Similarly to the above, when the sampling signals S3, S4 . . . ,and Sn have become the H level in sequence, the image signals VID1 toVID6 are respectively sampled onto the six data lines 114 belonging toeach of the sampling signals, and these image signals VID1 to VID6 arerespectively written into the six pixels intersecting with the scanningline 112 selected at that time. Thereafter, the next scanning line 112is selected, the sampling signals S1 to Sn are sequentially outputtedagain, and similar writing is iteratively executed.

[0073] In the sampling periods based on the H levels of the enablesignals ENB1, ENB2, noises are superposed on the image signals of therespective data lines. Especially, the influences of high frequencynoises ascribable to the clocks CLX, CLX_(inv) and the enable signalsENB1, ENB2 which rise and fall in units of the plurality of pixels inthe horizontal direction appear as line blurs in the vertical directionand incur the drastic degradation of an image quality.

[0074] In this exemplary embodiment, however, the start timing and endtiming of each sampling period based on the H level of the enable signalENB1 or ENB2 are set to be sufficiently distant from the rise and falltimings of the clocks CLX, CLX_(inv). Thus, the high frequency noisesascribable to the clocks CLX, CLX_(inv) and the enable signals ENB 1,ENB2 are large in periods other than the sampling periods and arecomparatively small in the sampling periods as shown in FIG. 5. The highfrequency noise ascribable to the clocks CLX, CLX_(inv) and the highfrequency noise ascribable to the enable signal ENB1 or ENB2 havesufficient distant generation timings, and noise of large levelresulting from the addition of both the noises does not develop, so thatthe level of noise to be mixed into the image signal is comparativelysmall.

[0075] In this manner, in the settings of this exemplary embodiment, therises and falls of the clocks CLX, CLX_(inv) are not generated in the Hlevel periods of the enable signals ENB1, ENB2 for setting the samplingperiods, and the rises and falls of the enable signals ENB1, ENB2 andthose of the clocks CLX, CLX_(inv) are generated at the sufficientlydistant timings, whereby the levels of the high frequency noises to bemixed into the image signals which are fed to the data lines are reducedto prevent the vertical direction line blurs from being displayed on ascreen and to enhance a screen quality.

[0076] The first exemplary embodiment is described above assuming thehorizontal scanning direction to be the rightward (R) direction. To thecontrary, in a case where the horizontal scanning direction is theleftward (L) direction, the construction of each latch circuit 1430 inthe R-direction transfer mode is bilaterally reversed. In this case,therefore, it is only different that the sampling signals are outputtedin the sequence of Sn, S(n−1) . . . , S2 and S1, and hence, theoperation shall be omitted from description. Also in a case where thevertical scanning period is in the up direction, the operation issimilar.

[0077] In the above description, the sampling circuit 150 is soconstructed that the image signals VID1 to VID6 converted into the sixloops are simultaneously sampled and fed to the six data lines 114forming one group, and that the image signals VID1 to VID6 aresequentially applied to the respective data line groups. However, thenumber of converted loops and the number of data lines to which theimage signals are simultaneously applied (that is, the number of datalines constituting one group) are not restricted to “6”. By way ofexample, if the response rate of each switch 151 in the sampling circuit150 is sufficiently high, a construction may well be adopted in whichthe image signals are serially transmitted to a single signal linewithout being deserialized, so as to be sequentially sampled onto therespective data lines 114. It is also allowed to adopt a construction inwhich the number of converted loops and the number of data lines towhich the image signals are simultaneously applied are set at, forexample, “3”, “12” or “24”, and 3-loop conversion, 12-loop conversion or24-loop conversion, for example, is performed for the data linesnumbering, for example, 3, 12 or 24, whereby the image signals fed inparallel are simultaneously fed. As the number of converted loops andthe number of data lines to which the image signals are simultaneouslyapplied, any multiple of “3” is favorable to simplify controls,circuits, etc., in relation to the fact that a color image signal iscomposed of signals based on three primary colors.

[0078] In the exemplary embodiment described above, the switchingelements of the pixels have been explained as 3-terminal elementsrepresented by the TFTs, but they may well be constructed of 2-terminalelements, such as diodes. However, in case of employing the 2-terminalelements as the switching elements of the pixels, it is necessary toform the scanning lines 112 on one substrate and the data lines 114 onthe other substrate, and to form the 2-terminal elements between eitherthe scanning lines 112 or the data lines 114 and the pixel electrodes118. In this case, each pixel is constituted by the pixel electrode 118to which the 2-terminal element is connected, the signal line (eitherthe data line 114 or the scanning line 112) which is formed on thecounter substrate, and the liquid crystal which is held between thepixel electrode and the signal line.

[0079] The above exemplary embodiment is described as to the example inwhich one enable signal ENB1 or ENB2 is generated for one clock CLX orCLX_(inv). Further, it is possible to adopt a method in which aplurality of enable signals ENB1, ENB2, . . . are generated for oneclock CLX or CLX_(inv) so as to feed image signals to a plurality ofdata lines in time division within one clock CLK period. FIG. 6 is atiming chart showing a clock CLK and enable signals ENB1 to ENB4 in thecase where image signals are fed to four data lines in time divisionwithin one clock CLK period.

[0080] As shown in FIG. 6, the enable signals ENB1, ENB2 are activatedin the H level period of the clock CLK, and the enable signals ENB3,ENB4 are activated in the L level period of the clock CLK. Accordingly,by using the enable signals ENB1 to ENB4, the image signalscorresponding to the four data lines can be sampled in time divisionwithin one cycle of the clock CLK so as to be fed to the fourcorresponding data lines.

[0081] Also in FIG. 6, neither the rise nor fall of the clock CLK isgenerated in the H level periods of the enable signals ENB1 to ENB4 toset sampling periods. Moreover, the rises and falls of the enablesignals ENB1 to ENB4 and those of the clock CLK are generated atsufficiently distant timings.

[0082] Thus, also in this case, the levels of high frequency noises tobe mixed into the image signals which are fed to the data lines can bereduced as shown in FIG. 6, thereby to reduce or prevent verticaldirection line blurs from being displayed on a screen and to enhance ascreen quality.

[0083] Incidentally, although the example adopting the liquid crystal asthe electro-optical substance has been described in the above exemplaryembodiment, the present invention is also applicable to a display devicewhich employs electro luminescent elements or the likes so as to presenta display on the basis of the electro-optical effect thereof. That is,the present invention is applicable to any electro-optical device, whichhas a construction similar to that of the foregoing liquid crystaldevice.

[0084] Cases are described below where the liquid crystal devicedescribed above is applied to each of various exemplary electronicequipment.

[0085] <#1: Projector>

[0086] A projector is described below which employs the liquid crystalpanel as a light valve. FIG. 7 is a plan view showing the constructionof the projector. As shown in FIG. 7, a lamp unit 1102 which includes awhite light source, such as halogen lamp, is disposed inside theprojector 1100. Projection light emitted from the lamp unit 1102 isdecomposed into three primary colors RGB by three mirrors 1106 and twodichroic mirrors 1108 which are arranged inside, and the lightcomponents R, G and B are respectively guided to the liquid crystalpanels 100R, 100G and 100B which serve as the light valves correspondingto the primary colors.

[0087] The light of the color B has an optical path which is longer ascompared with those of the lights of the other colors R and G, andhence, in order to reduce or prevent the loss thereof, it is guidedthrough a relay lens system 1121 which includes an entrance lens 1122, arelay lens 1123, and an exit lens 1124.

[0088] The liquid crystal panels 100R, 100B and 100G have constructionseach of which is equivalent to that of the liquid crystal panel 100described above, and they are respectively driven by primary colorsignals R, B, G which are fed from image signal processor circuits (notshown). Subsequently, the lights modulated by these liquid crystalpanels are entered into a dichroic prism 1112 from three directions. Inthe dichroic prism 1112, the lights of the colors R and B are refractedat 90 degrees, whereas the light of the color G proceeds rectilinearly.Accordingly, the images of the respective colors are composed, with theresult that a color image is projected on a screen 1120 through aprojection lens assembly 1114.

[0089] When focused on the display images based on the respective liquidcrystal panels 100R, 100B and 100G, the display image based on theliquid crystal panel 100G needs to be bilaterally inverted with respectto the display images based on the liquid crystal panels 100R and 100B.Therefore, horizontal scanning directions are in the relationship ofreverse directions to each other between in the liquid crystal panel100G and in each of the liquid crystal panels 100R, 100B. Since thelights corresponding to the respective primary colors R, B and G areentered into the liquid crystal panels 100R, 100B and 100G by thedichroic mirrors 1108, color filters need not be disposed.

[0090] <#2: Mobile Type Computer>

[0091] An example is described below in which the liquid crystal panelis applied to a personal computer of a mobile type. FIG. 8 is aperspective view showing the construction of this personal computer.Referring to FIG. 8, the computer 1200 is constructed of the bodyportion 1204 including a keyboard 1202, and a liquid-crystal displayunit 1206. This liquid-crystal display unit 1206 is constructed byadding a backlighting unit onto the rear side of the liquid crystalpanel 100 discussed above.

[0092] <#3: Portable Telephone>

[0093] An example is described below in which the liquid crystal panelis applied to a portable telephone. FIG. 9 is a perspective view showingthe construction of this portable telephone. Referring to FIG. 9, theportable telephone 1300 includes the liquid crystal panel 100 togetherwith a plurality of operating buttons 1302 and an earpiece 1304 as wellas a mouthpiece 1306. Also the liquid crystal panel 100 is furnishedwith a backlighting unit on its rear side as may be needed.

[0094] Apart from the electronic equipment described with reference toFIGS. 7 to 9, other types of electronic equipment include: a liquidcrystal television set, a video tape recorder of view finder type ormonitor direct-view type, a car navigation system, a pager, anelectronic notebook, a desktop calculator, a word processor, aworkstation, a video telephone, a POS terminal, an equipment including atouch panel, etc., for example.

[0095] The liquid crystal devices and further the electro-opticaldevices in the respective exemplary embodiments are applicable to theseand other various electronic equipment.

[0096] As described above, according to the present invention, thelogical status of a clock signal CLX or the inverted signal CLX_(inv)thereof is prevented from changing in an active enable signal period anda period vicinal thereto, thereby to bring forth the advantage that thelevel of noise to be mixed into an image signal can be lowered to reduceor suppress a vertical line blur.

What is claimed is:
 1. An electro-optical device, comprising: aplurality of scanning lines and a plurality of data lines; switchingelements disposed in correspondence with intersection parts between thescanning lines and the data lines; pixel electrodes disposed incorrespondence with the switching elements; video signal lines whichtransmit image signals; a data line drive device to sample the imagesignals transferred by the video signal lines and feed the signals tothe data lines, by using a clock which serves as reference of horizontalscanning and an enable signal which determines timings to feed the imagesignals to the data lines; and a timing generation device to set activeperiods of the enable signal which make the sampling of the imagesignals possible, in periods which do not include timings of rise orfall of the clock.
 2. The electro-optical device according to claim 1,the timing generation device setting the active periods of the enablesignal, in periods which are other than a period of predetermined widthincluding the timing of the rise or fall of the clock.
 3. Theelectro-optical device according to claim 2, the period of thepredetermined width being a period which is distant from the timing ofthe rise or fall of the clock more than 15 nanoseconds.
 4. Theelectro-optical device according to claim 1, the enable signal having aplurality of active periods within one cycle of the clock which servesas the reference of the horizontal scanning.
 5. An electro-opticaldevice, comprising: a plurality of scanning lines and a plurality ofdata lines; switching elements disposed in correspondence withintersection parts between the scanning lines and the data lines; pixelelectrodes disposed in correspondence with the switching elements; videosignal lines which transmit image signals; a data line driver circuitwhich samples the image signals transferred by the video signal linesand feed the signals to the data lines, by using a clock that serves asreference of horizontal scanning and an enable signal that determinestimings to feed the image signals to the data lines; and a timinggenerator circuit which sets those active periods of the enable signalthat make the sampling of the image signals possible, in periods that donot include timings of rise or fall of the clock.
 6. The electro-opticaldevice according to claim 5, the timing generator circuit setting theactive periods of the enable signal, in periods which are other than aperiod of predetermined width including the timing of the rise or fallof the clock.
 7. The electro-optical device according to claim 5, theenable signal having a plurality of active periods within one cycle ofthe clock which serves as the reference of the horizontal scanning.
 8. Adriver circuit for an electro-optical device, comprising: a data linedriver circuit which samples image signals transferred by video signallines and feeds the signals to the data lines, by using a clock thatserves as reference of horizontal scanning and an enable signal thatdetermines timings to feed the image signals to the data lines; and atiming generator circuit which setting those active periods of theenable signal that make the sampling of the image signals possible, inperiods that do not include timings of rise or fall of the clock.
 9. Thedriver circuit for an electro-optical device according to claim 8, thetiming generator circuit setting the active periods of the enablesignal, in periods which are other than a period of predetermined widthincluding the timing of the rise or fall of the clock.
 10. The drivercircuit for an electro-optical device according to claim 8, the enablesignal having a plurality of active periods within one cycle of theclock which serves as the reference of the horizontal scanning.
 11. Adrive method of driving an electro-optical device, comprising: feeding aclock which serves as a reference of horizontal scanning, and an enablesignal which determines timings to feed data lines with image signalstransferred by video signal lines; setting active periods of the enablesignal which make sampling of the image signals possible, in periodswhich do not include timings of rise or fall of the clock; and samplingthe image signals and feeding the signals to the data lines in theactive periods of the enable signal.
 12. The drive method of driving anelectro-optical device according to claim 11, timings of rise or fall ofthe clock and the active periods of the enable signal being periodswhich are distant from the timings of the rise or fall of the clock morethan 15 nanoseconds.
 13. An electronic equipment, comprising: theelectro-optical device according to claim 1 usable as an image formationdevice.